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RISC Operation

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  • Operation Buccaneer — On December 11, 2001, in an international operation known as Operation Buccaneer, law enforcement agents in six countries targeted 62 people suspected of software piracy, with leads in twenty other countries. U.S. law enforcement agents, led by… …   Wikipedia

  • RISC OS — Infobox OS name = RISC OS caption = A screenshot of RISC OS 4 developer = RISCOS Ltd (6.xx), Castle Technology Ltd / RISC OS Open Ltd (5.xx) source model = Proprietary software/Shared Source [ [http://www.iconbar.com/RISC OS Open Reveal Shared… …   Wikipedia

  • RISC — Reduced Instruction Set Computing (RISC) (engl. für Rechnen mit reduziertem Befehlssatz) ist eine bestimmte Designphilosophie für Prozessoren. Es steht im Gegensatz zum CISC Prozessor Design. Inhaltsverzeichnis 1 Konsequenzen des RISC… …   Deutsch Wikipedia

  • Classic RISC pipeline — In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000,… …   Wikipedia

  • Berkeley RISC — was one of two seminal research projects into RISC based microprocessor design taking place under ARPA s VLSI project. RISC was led by David Patterson at the University of California, Berkeley between 1980 and 1984, while the other was taking… …   Wikipedia

  • PA-RISC family — PA RISC is a microprocessor architecture developed by Hewlett Packard s Systems VLSI Technology Operation . As the name implies, it is an implementation using a RISC ( Reduced Instruction Set Computing ) design, where the PA stands for Precision… …   Wikipedia

  • PA-RISC — Microprocesador PA RISC 7300LC. PA RISC es el nombre por el que se conoce una arquitectura de microprocesadores desarrollada por sistemas Hewlett Packard y VLSI Technology Operation. Esta arquitectura se basa en el modelo RISC y en PA (Precision… …   Wikipedia Español

  • MIPS-RISC — MIPS R4400 Prozessor von Toshiba Die MIPS Architektur (Microprocessor without interlocked pipeline stages, etwa „Mikroprozessor ohne Pipeline Sperren“) ist eine RISC Prozessorarchitektur, die ab 1981 von John Hennessy und seinen Mitarbeitern an… …   Deutsch Wikipedia

  • Multiply–accumulate operation — In computing, especially digital signal processing, the multiply–accumulate operation is a common step that computes the product of two numbers and adds that product to an accumulator. The hardware unit that performs the operation is known as a… …   Wikipedia

  • PA-RISC — es como se conoce a una arquitectura de microprocesadores desarrollada por sistemas Hewlett Packard y VLSI Technology Operation. Como se puede deducir sólo con ver el nombre, esta arquitectura se basa en el modelo RISC y en PA (Precision… …   Enciclopedia Universal

  • Code opération — Langage machine Le langage machine, ou code machine, est la suite de bits qui est interprétée par le processeur d un ordinateur exécutant un programme informatique. C est le langage natif d un processeur, c est à dire le seul qu il puisse traiter …   Wikipédia en Français

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